1. Field of the Invention
The present invention relates to a semiconductor device having a high breakdown voltage transistor structure, and to a fabrication process therefor.
2. Description of the Related Art
High voltage operating transistors in semiconductor devices such as non-volatile semiconductor memories (e.g., flash memories) and liquid crystal drivers operative at a high voltage differ in structure from MOS transistors operative at an ordinary voltage. Such a transistor has substantially the same construction as an ordinary LDD-type MOS transistor but has a greater offset width than an ordinary sidewall spacer width in its LDD region (particularly, the greater offset width portion is called “offset region”).
More specifically, Japanese Unexamined Patent Publication No. 10(1998)-189954 discloses a novel high breakdown voltage transistor and a fabrication process therefor, in which an LDD offset region is formed by utilizing a double-layer gate electrode structure. The high breakdown voltage transistor can prevent deterioration of its driving performance, and employ a salicide process which is one of resistance reduction techniques.
A fabrication process for the high breakdown voltage transistor will be described with reference to FIGS. 14 to 17.
As shown in FIG. 14, a semiconductor substrate 21 having a device isolation oxide film (not shown) formed by a known device isolation process is first channel-doped, and then a first polysilicon layer 23 is formed on the substrate with the intervention of a gate insulation film 22.
In turn, a first gate electrode 24 is formed by a photolithography process as shown in FIG. 15. Then, a resist pattern (not shown) having an opening in a high breakdown voltage transistor formation region is formed on the resulting substrate, and LDD offset regions 25 of the high breakdown voltage transistor are formed in the substrate by ion implantation with the use of the resist pattern.
Thereafter, a second polysilicon film 27 is formed over the resulting substrate with the intervention of an intermediate insulation film 26 as shown in FIG. 16.
As shown in FIG. 17, a second gate electrode 28 is formed as covering the first gate electrode 24 by a photolithography process. Then, a resist pattern (not shown) having an opening in the high breakdown voltage transistor formation region is formed on the resulting substrate by a photolithography process, and ion implantation is performed with an energy such as not to allow ions to penetrate through the first and second gate electrodes 24, 28 for formation of source/drain regions 30.
For further micro-miniaturization of the device, wider diffusion of an impurity due to a heat treatment should be prevented. To this end, the heat treatment is carried out at a lower temperature in the fabrication process. Therefore, it is difficult to improve a junction breakdown voltage by broadening a diffusion profile by way of the heat treatment. In some cases, even the aforesaid high breakdown voltage transistor fails to satisfactorily ensure a required breakdown voltage.
An attempt may be made to form the source/drain regions at a sufficiently great junction depth by more deeply implanting impurity ions into the substrate with a higher energy. However, the gate electrode which is to be employed as a self-alignment mask for the ion implantation has a reduced thickness for improvement of micro-processability and for suppression of gate electrode depletion. Therefore, this attempt is useless.
In view of the foregoing, there is a demand for a high breakdown voltage transistor having a structure suitable for a micro-fabrication process, and a fabrication process for such a high breakdown voltage transistor.